£¨ÂÔ£©ÊÜÂò·½Î¯ÍжÔÏÂÁвúÎï¼°·þÎñ½øÐйú¼Ê¹«¿ªÕбꡣÏÖÑûÇëºÏ¸ñͶ±êÈ˲μÓͶ±ê¡£ Õбê²úÎïµÄÃû³Æ¡¢ÊýÁ¿¼°Ö÷Òª¼¼Êõ²ÎÊý£º ÐźſÉÊÓÐÔÔöÇ¿¹¤¾ß 1Ì× 1)¡¢¶¯Ì¬·ÂÕæÊǹó±Ê³Ò´¡ÑéÖ¤ÖеÄÖØÒª¼¼ÊõÊֶΣ¬Ò²ÊÇÕû¸öÑéÖ¤¹ý³ÌÖкÄʱ×î¶àµÄ¼¼Êõ»·½Ú£¬Òò´ËÔÚ·ÂÕæÑéÖ¤ÖÐÐèÒª½èÖú¿ÉÊÓÐÔÔöÇ¿¹¤¾ß£¬Ìá¸ßÄÚ²¿ÐźŵļàÊÓÄÜÁ¦£¬°ïÖú½øÐзÂÕæÎÊÌâµÄ·ÖÎöºÍ¶¨Î»£» 2)¡¢ÐźſÉÊÓÐÔÔöÇ¿¹¤¾ß£¬ÊÇÃæÏò·ÂÕæÆ÷µÄÐźſÉÊÓÐÔÔöÇ¿¹¤¾ß£¬Ö§³Ö³£¼ûµÄ·ÂÕæÆ÷£¬¾ß±¸¹ó³§¶ÙµþѹËõ¸ñʽµÄÐźŴ洢£¬Ö§³Ö³Õ±ð°ù¾±±ô´Ç²µ¡¢³Õ±á¶Ù³¢ºÍ³§²â²õ³Ù±ð³¾³Õ±ð°ù¾±±ô´Ç²µÓïÑÔ£¬¿ÉÒÔÌá¸ß·ÂÕæÔËÐÐËٶȺÍÐźŷÖÎöµÄЧÂÊ£» 3)¡¢Ö§³Ö³Õ±á¶Ù³¢¡¢³Õ±ð°ù¾±±ô´Ç²µ¼°»ìºÏÓïÑÔÉè¼Æ£¬Ö§³Ö³§²â²õ³Ù±ð³¾³Õ±ð°ù¾±±ô´Ç²µ¹¹½¨·ÂÕæ»·¾³°Õ±ð²õ³Ùµþ±ð²Ô³¦³ó£» 4)¡¢Ö§³ÖRTL¼¶ºÍÃż¶Éè¼Æ·ÂÕæ£¬Ö§³ÖÃż¶Íø±íµÄÐźſÉÊÓÐÔÔöÇ¿£»Ö§³Ö Cadence IES·ÂÕæÆ÷¡£ £¨ÂÔ£© ¹ºÂòÕбêÎļþʱ¼ä(ÖÐ/Ó¢ÎÄ)£º¼´ÈÕÆðÿÌìÉÏÎç9:00-16:00£¨±±¾©Ê±¼ä£¬½Ú¼ÙÈÕ³ýÍ⣩¡£ ¹ºÂòÕбêÎļþµØµã(ÖÐ/Ó¢ÎÄ)£º±±¾©Êи´ÐËÃÅÍâ´ó½Ö´¡2ºÅÖл¯´óÏÃһ¥´óÌüÎ÷²à Ͷ±ê½ØÖÁʱ¼äºÍ¿ª±êʱ¼ä£º2017Äê1ÔÂ23ÈÕ9:30 ¿ª±êµØµã(ÖÐ/Ó¢ÎÄ)£º±±¾©£¨ÂÔ£© £¨ÂÔ£© µç×Ó£¨ÂÔ£© £¨ÂÔ£© £¨ÂÔ£© ÈËÃñ±Ò¿ª»§ÒøÐÐ(ÖÐ/Ó¢ÎÄ)£º¹¤ÉÌÒøÐб±¾©³¤°²Ö§ÐÐ; . Õ£¨ÂÔ£© Íâ±Ò¿ª»§ÒøÐУºÖйúÒøÐйɷÝÓÐÏÞ¹«Ë¾±±¾©·ą֧́ÐÐ Õ£¨ÂÔ£© SWIFT Code: BKCH CN BJ 110 SINOCHEM International Tendering Co., Ltd., entrusted by the Buyer, hereby carries out public bid for the supply of the following goods and related services, and now invites eligible bidders to attend the bidding. Signal Visibility Enhancement Tool 1set 1). Dynamic simulation is an important technical measure in FPGA verification, also is the most time-consuming technology throughout the entire verification process, in order to monitor the internal signal in simulation, the simulator is required to monitor the whole process of internal signal, which consumes large quantities of resources, occupies a large amount of storage space and affect the simulation speed. Visibility enhancement tools are needed to use in the simulation verification, in order to improve the ability to monitor internal signals, and help to analyze and locate simulation problems; 2). Signal visibility enhancement tool is the one orienting the simulator, supports common simulators, with the signal storage of FSDB compression format, supports Verilog, VHDL and SystemVerilog languages, which can improve the simulation running speed and the efficiency of signal analysis; 3). Support VHDL, Verilog and mixed language design, and support SystemVerilog to build simulation environment TestBench; 4). Support RTL level and gate level design simulation, support signal visibility enhancement of gate level netlist£»Support IES Cadence simulator. Price of Bidding Document: RMB1000 or USD160 for each complete set of package. Bidding Document is non-refundable (if mail order, with additional RMB100.00 or USD15.00). Time for obtaining Bidding Documents: After Dec.30th 9:00~16:00 (Beijing Time) every day (excl. holidays). Place for obtaining Bidding Documents: West Side of the Lobby, SINOCHEM Tower, A2, Fuxingmenwai Dajie, Beijing 100045, P. R. China. Contact person: Mr. Wang Xiaobin, Phone: £¨ÂÔ£© Deadline of Bid Submission and Bid Opening Time: 9:00pm (Beijing Time), Jan.23th, 2017. SINOCHEM International Tendering Co., Ltd. Address: 20th Floor, SINOCHEM Tower, A2, Fuxingmenwai Dajie, Beijing 100045, P. R. China. Post code: 100045 Tel: £¨ÂÔ£© Fax: £¨ÂÔ£© Contact person: Mr. Wei Ping Bank Name: Industrial and Commercial Bank of China, Changan Branch Account no. (for documents purchase and bid security by RMB): £¨ÂÔ£©£¨ÂÔ£© Bank Name: Fengtai Branch, Beijing, Bank of China Account no. (for documents purchase by foreign currency): £¨ÂÔ£© Account no. (for bid security by foreign currency): £¨ÂÔ£© (USD), £¨ÂÔ£©(EUR), £¨ÂÔ£© (other foreign currencies) SWIFT Code: BKCH CN BJ 110
|
|